Negative bias temperature instability can severely affect the reliability of p-type metal-oxide-semiconductor field-effect transistors. In current CMOS fabrication processes, an anneal step at ~900°C – often referred to as the ‘reliability anneal’ – is typically performed to improve the dielectric quality and alleviate this issue.    However, in novel integration schemes such as sequential 3D stacking of multiple device tiers, such high-temperature steps might become inapplicable.    Ime...